Serial Peripheral Interface (SPI)
SPI is a master-slave architecture, usually with one Master (master device) and one or more Slave (slave device). There are four pins on the interface, and the docking method and hardware structure are as follows.
Pin name and meaning description
MOSI (Master Output, Slave Input): Master device data output, slave device data input
MISO (Master Input, Slave Output): Master device data input, slave device data output
SCLK (Serial Clock): Frequency signal, generated and controlled by the master device
CS/SS (Chip Select/Slave Select): Slave select signal, controlled by the master device; the slave device will only respond to the master device’s operation command when the CS signal is low potential
SPI interface, display data is transferred sequentially, QVGA 320 × 240 (pixels) for example, communication bandwidth is “320 × 240 × 16 bits (color depth) × 30 fps (frames per second) = 36.864 Mhz” Advantages – low cost: simple structure, low pin count, suitable for character type displays.
2.2 Integrated circuit interfacing bus (or I²C bus) (I²C):
Unlike the SPI’s point → point (or point → multi-point) structure, I²C is interfaced in a bus type, allowing multiple master devices and multiple slave devices to be connected in series at the same time, with the following interfacing method and hardware structure.
The I²C architecture is simpler than SPI, with only two signal lines: the data line (SDA, Serial Data Line) and the frequency line (SCL, Serial Clock Line), and the communication bandwidth is as follows.
Standard mode = 100K bit/s.
Full speed mode = 400K bit/s.
Fast mode = 1M bit/s.
High speed mode = 3.2M bit/s.
Advantages: early architecture, simple control, no need for frequency or synchronization signal; low power consumption, suitable for small size TFT display, such as 1.8″, 2.2″, 2.4″.
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